4GB LPDDR5X RS1G32LC5D4FDB-31BT electrical component distributors

Architecture
– 12.8 GB/s maximum bandwidth per channel
– Frequency range: 800–5 MHz (data rate range per pin: 6400–40 Mbp/s

with WCK:CK = 4:1)
– Selectable CKR (WCK:CK = 2:1 or 4:1)

LPDDR5 data interface
– Single x16 channel/die
– Double-data-rate command/address entry
– Differential command clocks (CK_t/CK_c) for high-speed operation
– Differential data clocks (WCK_t/WCK_c)
– Optional differential read strobe (RDQS_t/ RDQS_c)
– 16n-bit or 32n-bit prefetch architecture
– 4KB page size with 8-bank (8B mode), 2KB page size with bank group (BG mode), or 16-bank (16B mode) operation
– Command-selectable burst lengths (BL = 16 or 32) in bank group or 16-bank modes
– Background ZQ calibration/command-based ZQ calibration
– Optional link protection (link ECC)
– Partial-array self refresh (PASR) and partial-array auto refresh (PAAR) with segment mask

Ultra-low-voltage core and I/O power supplies
– VDD1 = 1.70–1.95V; 1.8V NOM
– VDD2H = 1.01–1.12V; 1.05V NOM
– VDD2L = VDD2H or 0.87–0.97V; 0.9V NOM
– VDDQ = 0.5V NOM or 0.3V NOM (ODT off)

I/O characteristics
– Interface-LVSTL 0.5/0.3
– I/O type: Low-swing single-ended, VSS terminated
– VOH-compensated output drive
– Programmable VSS on-die termination (ODT)
– Non target ODT support
– DVFSQ support

Low power features
– DVFSC: Dynamic voltage frequency scaling core
– Single-ended CK, single-ended WCK, and single- ended RDQS
VDD1/VDD2H/VDD2L/VDDQ（ODT on）/ (ODT off): 1.8V/1.05V/0.9V/0.5V/0.3V

Array configuration
– 512 Meg x 32 (2 channels x 16 I/O)
– 1Gig x 32 (2 channels x 16 I/O)

Device configuration
– 512M16 x 2 die in package
– 512M16 x 4 die in package

FBGA “green” package
– 315-ball FBGA (12.4mm x15mm Seated height: 1.1mm MAX)

Speed grade, cycle time (tWCK)
– 6400 Mb/s

Operating temperature range
– -25°C to + 85°C

Related applications
Laptop
mobile phone
vehicle